Tbf, I am not a grey beard chief engineer, and I strongly prefer VHDL for design. For verification I actually really like SystemVerilog.
VHDL is strongly types, which prevents a lot of issues with types that I’ve hit with [System]Verilog.
Also, having learned VHDL first, I think it is easier to go from VHDL to Verilog, as opposed to vice versa. And this is mainly because VHDL is stricter.
Tbf, I am not a grey beard chief engineer, and I strongly prefer VHDL for design. For verification I actually really like SystemVerilog.
VHDL is strongly types, which prevents a lot of issues with types that I’ve hit with [System]Verilog.
Also, having learned VHDL first, I think it is easier to go from VHDL to Verilog, as opposed to vice versa. And this is mainly because VHDL is stricter.